1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus that restricts a refresh operation while synchronizing an internal clock with an external clock.
2. Related Art
In general, semiconductor memory apparatuses use a DLL (Delay Locked Loop) or a PLL (Phase Locked Loop) as a clock synchronizer for compensating skew between data and a clock signal input from the outside or between an external clock signal and an internal clock signal.
For example, a DLL includes: an input buffer which receives and outputs an external clock signal; a delay unit which receives a clock signal output by the input buffer and outputs an internal clock signal which is delayed under the control of a phase detector; a delay modeling unit which delays the internal clock signal output by the delay unit on the basis of a modeling result according to a real path of the external clock signal, and outputs the delayed clock signal; and the phase detector which compares phases between an output signal of the delay modeling unit and an output signal of the input buffer.
When the clock signal output from the input buffer has the same phase as the output signal for the delay modeling unit, the delay unit does not adjust the delay time of the input clock signal, as a result, a locking operation is completed. The locking operation of the DLL should be performed within a predetermined time (for example, 200 cycles) after a DLL enable command and a DLL reset command are input.
In the semiconductor memory apparatus, after data is stored in memory cells, a leakage current occurs over time and data is lost as a result. For this reason, an operation for rewriting data, that is, a refresh operation should be performed.
FIG. 1 is a block diagram illustrating the construction of a general semiconductor memory apparatus.
As shown in FIG. 1, a clock buffer 110 receives an external clock signal CLK and an external clock enable signal CKE, converts the received signals into an internal clock signal ICLK and an internal enable signal ICKE each of which has a level suitable for an internal circuit, and outputs the internal signals. A command buffer 120 receives command signals /WE, /CAS, /RAS, and /CS from outside of the memory apparatus, converts the command signals into internal command signals each having a level suitable for the internal circuit, and outputs the internal command signals to a command decoder 140. An address buffer 130 receives address signals A0 to AN from the outside of the memory apparatus, converts the address signals into internal address signals each having a level suitable for the internal circuit, and outputs the internal address signals.
The command decoder 140 outputs an operation command signal CMD such as a refresh command signal REF, an active command signal (not shown), a pre-charge command signal (not shown), a write command signal (not shown), a read command signal (not shown), and so on, a mode-register-set command signal MRS_CMD, and an extended mode-register-set command signal EMRS_CMD by using the internal command signals received from the command buffer 120. The mode-register-set command signal MRS_CMD and the extended mode-register-set command signal EMRS_CMD become an input to a mode register 150.
The mode register 150 outputs a mode-register-setting signal MRS and an extended mode-register-setting signal EMRS (see FIG. 2) in response to output signals of the address buffer 130 and the mode-register-set command signal MRS_CMD and the extended mode-register-set command signal EMRS_CMD output from the command decoder 140. In particular, the extended mode-register-setting signal EMRS is used to drive the clock synchronizing unit 160, such as a DLL or a PLL, with an enable signal EN. The mode-register-setting signal MRS is used to reset the clock synchronizing unit 160 with a reset signal RESET (not shown). In response to the enable signal EN and the reset signal RESET inputted by the mode register 150, the clock synchronizing unit 160 completes a locking operation within a predetermined time and outputs a lock-completion signal LOCK and a synchronized clock signal LCLK.
The semiconductor memory apparatus performs a refresh operation on the basis of the refresh command signal REF among the command signals outputted from the command decoder 140.
In this way, the semiconductor memory apparatus according to the related art performs a refresh operation regardless of the operational state of the clock synchronizing unit 160. However, if the clock synchronizing unit 160 is reset and the refresh command signal is applied before the locking operation is completed, noise generated during the refresh operation can disturb the locking operation such that the locking operation cannot be completed within the predetermined time.
FIG. 2 is a timing diagram illustrating a refresh operation when the general semiconductor memory apparatus performs internal clock synchronization.
As shown in FIG. 2, when the enable signal EN of the extended mode-register-setting signal EMRS outputted from the mode register 150 is enabled, the clock synchronizing unit is driven. Furthermore, after the reset signal RESET of the mode-register-setting signal MRS is enabled, the clock synchronizing unit 160 should complete the locking operation within the predetermined time. However, the refresh command signal REF is applied from the command decoder 140 regardless of the above-mentioned operation of the clock synchronizing unit 160.
Therefore, when the clock synchronizing unit 160 is reset but the clock synchronizing unit 160 does not complete a locking operation, the refresh operation for the semiconductor memory apparatus is performed, thereby generating power supply noise. The power supply noise may make it difficult to smoothly complete the locking operation.